Variable size First In First Out (FIFO) memory with head and tail caching
US6987775B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 15, 2001 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Oct 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/108
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A variable size first in first out (FIFO) memory is provided. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.