Method and apparatus for synchronization of clock domains
US6988215B2 · kind B2 · utility
22Cited by
8References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2001 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Oct 11, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for synchronizing clock domains. A slow clock signal is received. A circuit in a slow clock domain is operated based upon the slow clock signal. A fast clock signal is received. The slow clock signal is synchronized using the fast clock signal. The operation of the circuit is modified from the slow clock domain to the fast clock domain, modifying the operation comprising changing a clock operation frequency during a non-transition period of the slow clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.