Method and apparatus for processing control using a multiple redundant processor control system
US6988221B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2004 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | May 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for synchronizing a plurality of main processors. At a first time and in response to a first time reference, a first rendezvous signal is sent from a first to a second of the plurality of main processors. At a second time, and in response to a second time reference, a second rendezvous signal is sent from the second of the plurality of main processors, to the first of said plurality of main processors. After the first rendezvous signal is received by the second of the plurality of main processors and the second rendezvous signal is received by the first of said plurality of main processors, substantially simultaneous scanning of control information is initiated by the first and second of the plurality of main processors. In variations, a difference between the first and second times signals a fault condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.