Process for laminating a dielectric layer onto a semiconductor
US6989336B2 · kind B2 · utility
1Cited by
4References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2004 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Oct 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K10/468
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention relates to processes useful for fabricating electronic devices, more particularly to a process for laminating a layer of dielectric material onto a semiconductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.