Test structure for determining a minimum tunnel opening size in a non-volatile memory
US6989551B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2001 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Aug 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a test structure far testing the sufficiency of tunnel opening sizes in a non-volatile memory cell includes N write paths aligned substantially in parallel, each of the write paths beings individually programmable and M floating gates, each of the floating gates overlapping each of the multiple write paths to form a N column-by-M row array of Intersecting areas. An N column-by-M row array of tunnel openings is formed in the intersecting areas and between the floating gates and write paths, with the tunnel openings in each array column being of a same size and the tunnel openings in each array row being of different sizes. A read path coupled to the M floating gates is operable to detect a programmed write path if the tunnel openings formed over the programmed write path are of sufficient size to successfully couple the M floating gates to the programmed write path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.