Apparatus and method for reducing power consumption by a data synchronizer
US6989695B2 · kind B2 · utility
14Cited by
16References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2003 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Feb 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes at least one logic storage unit which has a clock input. The apparatus also includes a logic circuit associated with the at least one logic storage unit. The logic circuit is capable of selectively preventing a clock signal from being applied to the clock input of the at least one logic storage unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.