Non-quasistatic phase lock loop frequency divider circuit
US6989697B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2005 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Jan 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A non-quasistatic MOS frequency divider circuit uses a phase lock loop configuration including an antenna coil to induce a differential input signal, an antenna resonating capacitor, a rectifier, a voltage controlled ring oscillator, a phase detector and a loop filter. All transistors used are organic MOS devices of PMOS, NMOS or both PMOS and NMOS varieties. The voltage-controlled oscillator includes a multiple delay stage ring oscillator. The phase detector includes transistors connected as sampling switches to sample the individual oscillator stage voltages into the loop filter. The sampling transistors have gates connected to the coil. The loop filter provides a substantially direct current to a loop amplifier and then to the voltage controlled oscillator delay control input. This configuration results in the voltage controlled oscillator frequency being synchronous to—and at a sub-multiple of the antenna signal frequency. The sampling transistor gates are all connected to the coil and thereby become part of the capacitance of the radio frequency parallel resonant network. The transistor gates are then efficiently switched at the rate of the radio frequency signal with no delay…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.