Active ESD shunt with transistor feedback to reduce latch-up susceptibility
US6989979B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2003 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | May 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/819
Abstract
A VDD-to-VSS clamp shunts current from a power node to a ground node within an integrated circuit chip when an electro-static-discharges (ESD) event occurs. A resistor and capacitor in series between power and ground generates a low voltage on a trigger node between the resistor and capacitor when an ESD event occurs. A p-channel transistor with its gate driven by the trigger node turns on, driving a gate node high. The gate node is the gate of an n-channel shunt transistor that shunts ESD current from power to ground. A p-channel feedback transistor terminates the ESD shunt current. The p-channel feedback transistor is connected between power and the trigger node, in parallel with the resistor, and has the gate node as its gate. When a latch up trigger occurs, such as electron injection, voltage drops across an N-well of the resistor is prevented by the parallel p-channel feed-back transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.