Multiple match detection circuit and method
US6990001B2 · kind B2 · utility
8Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2001 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Jun 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search-and-compare operation, and to set the circuit to a precharge state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.