Method and apparatus for multiple row caches per bank
US6990036B2 · kind B2 · utility
1Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Dec 30, 2003 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Dec 30, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to write the data directed to at least one row through a write operation causing the data to written to the row of sense amplifiers versus from the row of memory cells, directly, and to store an indication that the data cached by the row of sense amplifiers is dirty.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.