Semiconductor integrated circuit device having a common DRAM block accessed by a plurality of logic circuits
US6990043B2 · kind B2 · utility
28Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2005 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Mar 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of logic circuits access a DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.