Apparatus and method for acquiring phase lock timing recovery in a partial response maximum likelihood (PRML) channel
US6990163B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 6, 2001 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Oct 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is a method of acquiring phase lock to a data signal in a digital channel having a digital feedback loop. The method generally comprises: (A) applying the data signal to an analog phase lock loop configured to have (i) at least two poles and (ii) presend intermediate output signal frequency locked to the data signal; (B) applying the data signal and the intermediate output signal to the digital channel; and (C) adjusting a delay constant for the digital feedback loop to (i) compensate for variations in phase between the data signal and the intermediate output signal and (ii) acquire phase lock by using a single pole in the digital channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.