High performance carry chain with reduced macrocell logic and fast carry lookahead
US6990508B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2001 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Mar 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic block in an integrated circuit comprising a plurality of macrocells, an AND-array, an OR-array, and a logic circuit. The plurality of macrocells may comprise logic that may be configured to (i) generate and propagate an inverted carry-input signal and (ii) generate a sum bit. The AND-array may comprise at least two product terms per macrocell. The OR-array may be configured to generate a sum-of-products term for each macrocell in response to the two product terms. The logic circuit may be configured to (a) receive (i) the product terms and (ii) the carry-input signal generated by a first macrocell of the plurality of macrocells and (b) generate (i) a block carry-propagate signal, (ii) a block carry-generate signal, and (iii) a block carry-output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.