Processor with a computer repeat instruction
US6990570B2 · kind B2 · utility
8Cited by
24References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1999 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Oct 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing engine, such as a digital signal processor, includes an execution mechanism, a repeat count register and a repeat count index register. The execution mechanism is operable for a repeat instruction to initialize the repeat count index register with the content of the repeat count register, and to modify the content of the repeat count register. The repeat instruction comprises two parts, the first of which initializes the repeat count index register and initiates repeat of a subsequent instruction, and the second part of which modifies the content of the repeat count register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.