High speed syndrome-based FEC encoder and decoder and system using same
US6990624B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 12, 2001 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Sep 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.