Variable stage ratio buffer insertion for noise optimization in a logic network
US6990647B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 2002 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Jun 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer for use in a logic circuit comprises input and output nodes. A first inverter having a first device size is coupled to the input node. A second inverter is coupled in series with the first inverter and with the output node. The second inverter having a second device size at least six times greater than the first device size. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.