Process of forming high-k gate dielectric layer for metal oxide semiconductor transistor
US6991989B2 · kind B2 · utility
3Cited by
3References
13Claims
0Family size
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Key dates
| Filing date | May 5, 2004 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | May 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process of forming a high-k gate dielectric layer is applied in forming semiconductor devices such as metal oxide semiconductor transistor or memory devices. A metal layer such as Hf or Zr is formed on a substrate. The substrate is then dipped in an acidic solution such as a nitric acid aqueous solution to form a high-K metal oxide layer including oxides or silicate with a predetermined thickness. Thereby, leakage current is effectively reduced to meet the requirement of currently technology nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.