Monitor pattern of semiconductor device and method of manufacturing semiconductor device
US6992327B2 · kind B2 · utility
5Cited by
10References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2003 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Jun 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.