Apparatus and method for DC offset reduction
US6992526B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2004 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Mar 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/411
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A feedback system has a settling time that is independent of the forward gain of the amplifier stage, and a feedback path that is responsive to the magnitude of DC offset in the output signal. Settling time may be made independent of the forward gain of the amplifier stage by providing a constant loop gain in the amplifier stage through active gain control of both the forward and linear feedback amplifier elements. The feedback path may be made responsive to the magnitude of DC offset in the output signal by providing a non-linear transconductance in the feedback path that varies the high pass corner and hence the DC offset reduction time of the amplifier stage in response the magnitude of DC offset in the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.