Phase-locked loop circuit for reproducing a channel clock
US6992958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2001 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Mar 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1262
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In PLL circuits for reproducing a channel clock in synchronism with data read from a disk-shaped recording medium driven for rotation, the frequency dividing ratio of frequency dividers provided in desired signal paths is made changeable according to the reproduced signal format of a CD reproduced signal or a DVD reproduced signal, for example. Although the frequency of the channel clock in synchronism with the reproduced signal differs in different signal formats, the above configuration makes it possible to reproduce the channel clock properly in accordance with a plurality of signal formats only by the operation of changing the frequency dividing ratio in a PLL circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.