Distributed switch memory architecture
US6993020B2 · kind B2 · utility
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3References
24Claims
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Key dates
| Filing date | Nov 6, 2003 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Dec 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A distributed memory switch system for transmitting packets from source ports to destination ports, comprising: a plurality of ports including a source port and a destination port wherein a packet is transmitted from the source port to the destination port; a memory pool; and an interconnection stage coupled between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be transmitted from the source port to the destination port via the memory pool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.