Communications receiver architectures and algorithms permitting hardware adjustments for optimizing performance
US6993099B2 · kind B2 · utility
4Cited by
4References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2001 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Jan 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver architecture featuring a decimation filter and a bypass around said decimation filter is disclosed along with a method for optimizing said receiver's sampling phase and programmable gain amplifier. Said method utilizes said receiver architecture to modify said receiver's receive path to simplify optimizations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.