Digital phase locked loop with programmable digital filter
US6993108B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2001 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Dec 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a digital filter of a DPLL (digital phase locked loop) for minimizing the bit error rate for multiple communications protocols, a first reloadable register portion stores a TBW (total bandwidth) value programmed into the first reloadable register portion through a first port, and a second reloadable register portion stores a DBW (differential bandwidth) value programmed into the second reloadable register portion through a second port. An up—counter generates an UP—CNT value by counting up each UP signal pulse generated by a phase transition detector when a first phase of a SDIN (serial data input) signal leads a second phase of a current ACLK (recovered clock) signal. A down—counter generates a DOWN—CNT value by counting up each DOWN signal pulse generated by the phase transition detector when the first phase of the SDIN (serial data input) signal lags the second phase of the current ACLK (recovered clock) signal. One of a FWD (forward) signal or a BWD (backward) signal are asserted or are both not asserted depending on the UP—CNT value and the DN—CNT value in comparison to the TBW value and the DBW value. Another clock signal having a leading phase from the current ACLK signal…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.