Zero-delay buffer circuit for a spread spectrum clock system and method therefor
US6993109B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2002 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Oct 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2215/067
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.