High speed clock divider with synchronous phase start-up over physically distributed space
US6993671B2 · kind B2 · utility
8Cited by
11References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 28, 2003 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Feb 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method that controls the start time of different clocks in different clock domains, each of which is controlling an I/O, provides that the first cycle of each time domain is within a predetermined timing delay of one another. Reset signals are pipelined across the clock domains such that all the clocks trigger at substantially the same time. The clock channels may be arranged logically and physically in n groups of m channels with delays associated with each n group according to the relative position of the n group within the sequence of the n groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.