Radix-N architecture for deinterleaver-depuncturer block
US6993702B2 · kind B2 · utility
3Cited by
3References
3Claims
0Family size
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Key dates
| Filing date | Dec 18, 2002 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Nov 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A de-interleaver-de-puncturer architecture is scalable and capable of achieving a higher data throughput than that achievable using a conventional disjointed de-interleaver-de-puncturer architecture. The higher data throughput is achieved without increasing the clock speed of the de-interleaver. The scalable de-interleaver-de-puncturer architecture is also less complex than a conventional disjointed de-interleaver-de-puncturer architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.