Pending bug monitors for efficient processor development and debug
US6993736B2 · kind B2 · utility
5Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2003 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Jul 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention addresses difficult issues encountered in simulations and design verification efforts on complex microprocessor/digital signal processor devices. The invention provides a means for monitoring and tracking pending bugs and automates the rejection of already known/pending bugs. This allows developers/debuggers to focus on finding and correcting new bugs. This improves design development efficiency many fold and lets design engineers and verification engineers focus on real, new and unique issues. This is especially true when test cases are generated in a random way and the test case contents are actually unknown.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.