Method and apparatus for electrostatically aligning integrated circuits
US6995039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2004 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Jun 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that uses electrostatic forces to align semiconductor chips relative to each other. The system operates by fabricating a first set of conductors on the top surface of a first chip and fabricating a corresponding second set of conductors on the top surface of a second chip. To align the chips, the system electrically charges the first set of conductors and the second set of conductors. The system also places the first chip face-to-face with the second chip, so that the first set of conductors is in close proximity to the second set of conductors. This allows electrostatic forces between the first set of conductors and the second set of conductors to bring the first chip into alignment with the second chip and to hold them in place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.