Thin film transistor panel liquid crystal display
US6995394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2003 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Mar 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array panel is provided, which includes: a pair of first and second gate lines; a data line intersecting the gate lines in an insulating manner; a storage electrode line supplied with a common voltage; a pixel electrode formed in a pixel area defined by the intersections of the first and the second gate lines and the data line and including a plurality of subareas partitioned by cutouts; a direction control electrode formed in the pixel area and including a portion overlapping at least one of the cutouts; a first thin film transistor connected to the pixel electrode, the first signal line, and the third signal line; a second thin film transistor connected to the pixel electrode, the second signal line, and the third signal line; and a third thin film transistor connected to the direction control electrode, the second signal line, and the fourth signal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.