First-in first-out memory system with single bit collision detection
US6996015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2003 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Jun 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device (10). The device comprises a memory structure (12) structure comprising an integer M of word storage locations. The device further comprises a shift register (SRRD; SRWT) for storing a sequence of bits. The sequence in the shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a clock cycle to the shift register for selected data operations with respect to any of the word storage locations. The selected data operations are a data read or a data write. In response to each clock cycle, received from the circuitry for providing the clock cycle, the shift register shifts the sequence. Further, one bit in the sequence corresponds to an indication of one of the memory word storage locations from which a word will be read or into which a word will be written.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.