Enabling verification of a minimal level sensitive timing abstraction model
US6996515B1 · kind B1 · utility
20Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2001 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Sep 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a corresponding apparatus for verifying a minimal level sensitive timing abstraction model provides for an extension of the timing abstraction model. The method modifies and runs the timing abstraction model with certain stimulus to establish whether the timing results with the timing abstraction model are identical to the timing result with the modeled circuit. The timing abstraction model extension, which enables verification of the timing abstraction model, only negligibly increases the size of the timing abstraction model, thus keeping STA runtimes short and the memory requirements small.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.