Systems and methods for generating multiple transaction identifiers to reduced latency in computer architecture
US6996654B2 · kind B2 · utility
2Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 2003 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Feb 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods generate transaction identifiers. A plurality of available transaction identifiers are generated for use in identifying future transactions from a first bus. A new transaction identifier is generated upon receipt of each received transaction from the first bus. One of the available transaction identifiers is assigned to each received transaction prior to generation of the new transaction identifier so that the received transaction communicated on a second bus is identified by the one transaction identifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.