Content addressable memory array having flexible priority support
US6996662B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2001 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | May 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/742
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for processing addresses having variable prefix lengths, including (1) applying an input address to a plurality of CAM blocks; (2) assigning different sets of CAM blocks to store prefixes of different lengths; (3) generating a hit signal and an index signal with each of the CAM blocks in response to the input address; (4) programming a plurality of routing values; (5) routing the hit signals to a priority encoder in an order determined by the routing values; (6) generating an output hit signal with the priority encoder in response to the hit signals; (7) selecting one of the routing values as an index routing value in response to the output hit signal; and (8) routing one of the index signals as an output index value in response to the index routing value. Circuitry for implementing the method is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.