Patent · US Expired

Method and apparatus for protecting memory stacks

US6996677B2 · kind B2 · utility

22Cited by
8References
15Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 20, 2003
Grant dateFeb 7, 2006
Priority date
Expiry dateMay 5, 2024

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F21/52
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Method and apparatus for protecting processing elements from buffer overflow attacks are provided. The apparatus includes a memory stack for, upon execution of a jump to subroutine, storing a return address in a first location in a stack memory. A second location separate from the stack memory for storing an address of the first location and a third location separate from the stack memory for storing the return address itself are included. A first comparator upon completion of the subroutine, compares the address stored in the second location to the first location in the stack memory and a first interrupt generator provides an interrupt signal if locations are not the same. A second comparator looks at the return address stored in the third location and the return address stored in the first location in the stack memory and has a second interrupt generator for generating an interrupt signal if addresses are not the same. A further method and apparatus for protecting processing elements from buffer overflow attacks includes a memory stack for, upon execution of a jump to subroutine in a first processor, storing a return address in a first location in a stack memory and a second loca…

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.