Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention
US6996702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Oct 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/57
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.