Process for shutting down a CPU in a SMP configuration
US6996745B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2001 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Jun 6, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A symmetric multiprocessor (SMP) system includes a plurality of central processing units (CPUs). Processing by a central processing unit (CPU) is safely halted i.e., a CPU is shut down, using a technique that assures that the CPU is executing an idle thread when the CPU is shut down. Halting the CPU safely means (a) that the CPU cannot be executing a thread other than the idle thread, and (b) that state information for a thread does not reside only within the CPU. The first limitation assures that the CPU cannot be executing a time critical thread that fails if the execution of the time critical thread has to move to another CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.