Memory configuration scheme enabling parallel decoding of turbo codes
US6996767B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2002 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Nov 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3972
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory configuration scheme that enables parallel decoding of a single block of turbo-encoded data is described. In this scheme a single code block is divided into multiple subblocks and decoding is performed on subblocks in parallel. The turbo decoder memory is configured so that subblock decoders can access the common memory resources independently of each other. This scheme is different from existing parallel decoding schemes in that it achieves the parallel implementation by applying multiple decoders to a single code block, not by assigning multiple decoders to multiple code blocks. The advantages of this scheme include minimum memory requirement and minimum decoding latency. The minimum memory requirement results from the fact that it needs memory resources only for a single code block regardless of the number of decoders used. The decoding latency is minimum since decoding of a code block is over when decoding on subblocks is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.