Color filter configuration for a silicon wafer to be diced into photosensitive chips
US6998595B2 · kind B2 · utility
0Cited by
12References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 8, 2001 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Feb 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8057
Abstract
An architecture and manufacturing method for photosensitive chips, such as used in office equipment and digital cameras, involves creating grooves between chip areas in a wafer, and then placing a light-transmissive planar layer over the main surface of the wafer. The planar layer, which may be acrylic-based, creates a substantially planar surface over both the photosites in the chip areas and the grooves. The planar layer in turn supports one or more light-transmissive filtering layers. The arrangement avoids damage to the filtering layers when the wafer is diced along the grooves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.