Power grid layout techniques on integrated circuits
US6998719B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2003 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Jul 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for reducing power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to bond pads that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage VDD and a low power supply voltage VSS. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.