Subranging analog-to-digital converter with integrating sample-and-hold
US6999019B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 2004 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Apr 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A subranging analog-to-digital converter (ADC) includes an integrating sample-and-hold circuit. The integrating sample-and-hold circuit is configured to sample an input voltage by charging at least one capacitor by coupling a current proportional to the input voltage to the at least one capacitor. A coarsely-quantizing ADC is configured to convert the voltage on the at least one capacitor to a digitized value. A digital-to-analog converter is configured to convert the digitized value to an analog voltage. A finely-quantizing ADC is configured to convert the difference between the analog voltage and the voltage on the charged at least one capacitor in the integrating sample-and-hold circuit to another digitized value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.