Decoding circuit and method of Viterbi decoder
US6999532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2001 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Feb 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/2562
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a decoding circuit and a decoding method of a Viterbi decoder. The decoding circuit of the Viterbi decoder includes a branch metric unit, an add-compare-select unit and a path memory unit. The path memory unit includes a data string controller, a trace write-in register array, an idling register array and a decoding register array. In this invention, a run length limited code is used for effectively solving the problem of generating a complicated trellis diagram after the trellis diagram of the Viterbi decoder is subjected to a longitudinal arrangement. In addition, the register array can perform other operations at different times. Accordingly, a high decoding speed of the Viterbi decoder can be achieved without requiring a lot of registers for data processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.