Data ready indicator between different clock domains
US6999542B1 · kind B1 · utility
9Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2001 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Sep 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus including a first circuit and a second circuit. The first circuit may be configured to present a first data signal and a first indicator signal in response to a first clock signal and an enable signal. The second circuit may be configured to present a second data signal and a second indicator signal in response to the first data signal, the first indicator signal and a second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.