System and method for reducing the effects of clock harmonic frequencies
US6999723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2001 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Nov 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2215/065
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system and a method are provided for reducing the effects of spurious frequencies in a wireless communications device. The system comprises a processor having a reference frequency input and a clock having an output connected to the processor input. The clock supplies a clock frequency, or reference frequency, to the processor. The reference frequency is the frequency at which the processor operates. The clock also has an input for selecting a reference frequency to provide to the processor. The system also includes a transceiver having a plurality of selectable communications passbands. If the wireless communications device is a telephone, for example, the transceiver frequency (passband) may change as a function of the mode in which the phone is operating (AMPS, PCS, GSM, CDMA, or W-CDMA). In response to changing operating modes (transceiver passband), the clock frequency is adjusted. The clock frequency is selected so that harmonic frequencies associated with the clock frequency do not substantially interfere with the transceiver passband.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.