System and method for testing memory
US7000159B2 · kind B2 · utility
3Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2003 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Jul 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for reducing the amount of time for a boot operation is provided that includes a test management module that divides the memory into multiple test blocks and then selects a limited number of test blocks to test during a boot operation, thereby decreasing the overall amount of memory test time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.