Integrated circuit and method of manufacturing an integrated circuit and package
US7001834B2 · kind B2 · utility
4Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2003 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Apr 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.