Area efficient asymmetric cellular CMOS array
US7002192B2 · kind B2 · utility
2Cited by
3References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 7, 2004 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Dec 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
A cellular MOS array becomes denser by employing an asymmetric structure, in which the areas of the sources are reduced without changing the length and the width of the channel thereof, and thereby the chip size is reduced and the cost is lowered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.