Electrostatic discharge mitigation structure and methods thereof using a dissipative capacitor with voltage dependent resistive material
US7002217B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 2004 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Sep 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/162
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to structures and methods that reduce ESD damage to electronic devices. In an embodiment, the structure is a parallel plate dissipative capacitor formed by sandwiching a dissipative dielectric layer between two conductive layers in series to the electronic device. The dissipative dielectric layer includes a nonconductive dielectric doped with a voltage dependent resistive material that defines a conductive threshold voltage. The structure functions as a voltage dependent resistor in response to an applied voltage such as an ESD surge voltage exceeding the defined conductive threshold voltage and dissipates the applied voltage into thermal energy before it can reach the electronic device and cause damage. The dissipative dielectric layer restores to a dielectric and the structure functions as a capacitor when the excess voltage is depleted that is drops below the defined conductive threshold voltage. In another embodiment, the structure is a parallel plate dissipative capacitors in series that enhances ESD mitigation through a capacitive voltage divider structure. The structures can be used in EMI/RFI shielding applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.