Control signal generation for a low jitter switched-capacitor frequency synthesizer
US7002418B2 · kind B2 · utility
6Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2004 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | May 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0893
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.