Metal programmable phase-locked loop
US7002419B2 · kind B2 · utility
4Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2003 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Feb 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop within an integrated circuit assembly is provided. The phase-locked loop includes a plurality of subcells of semiconductor devices arranged in a base layer pattern on base layers of the integrated circuit assembly. One or more metal layers are formed over and interconnect the plurality of semiconductor devices in a metallization pattern. The phase-locked loop has an output frequency range that is changeable with a change to the metallization pattern without a corresponding change to the base layer pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.