Boolean logic tree reduction circuit
US7002493B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2004 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Jun 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions. Each bit has one of first and second complementary logic states. A modified data word is formed by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word. The number of bit positions in the first and second sets is greater than or equal to zero. A result of the Boolean logic tree function is generated based on a pattern of the first and second logic states in the modified data word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.